Editing ECE 2031
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== Topic List == |
== Topic List == |
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* CAD Tools |
* CAD Tools |
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β | * Logic Synthesis using an |
+ | * Logic Synthesis using an HDL |
* HDL models of basic gates and logic operations |
* HDL models of basic gates and logic operations |
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β | * Combinational design using multiple methods: primitive gates, schematic capture for |
+ | * Combinational design using multiple methods: primitive gates, schematic capture for FPGAs, and VHDL |
* HDL based simulation and synthesis with FPGAs |
* HDL based simulation and synthesis with FPGAs |
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* Examination of real timing issues on hardware using timing simulation, oscilloscope, and logic analyzer |
* Examination of real timing issues on hardware using timing simulation, oscilloscope, and logic analyzer |