Difference between revisions of "ECE 2031"

From Georgia Tech Student Wiki
m (add citation for devices thread requirement)
m (add wikipedia links for some acronyms. coming from a cs-perspective, these are acronyms I didn't know before i took this class)
 
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== Topic List ==
 
== Topic List ==
 
* CAD Tools
 
* CAD Tools
* Logic Synthesis using an HDL
+
* Logic Synthesis using an [[wikipedia:Hardware_description_language|HDL]]
 
* HDL models of basic gates and logic operations
 
* HDL models of basic gates and logic operations
* Combinational design using multiple methods: primitive gates, schematic capture for FPGAs, and VHDL
+
* Combinational design using multiple methods: primitive gates, schematic capture for [[wikipedia:Field-programmable_gate_array|FPGA]]<nowiki/>s, and VHDL
 
* HDL based simulation and synthesis with FPGAs
 
* HDL based simulation and synthesis with FPGAs
 
* Examination of real timing issues on hardware using timing simulation, oscilloscope, and logic analyzer
 
* Examination of real timing issues on hardware using timing simulation, oscilloscope, and logic analyzer

Latest revision as of 22:21, 31 December 2021

A large brick building with pavilion.
The College of Computing Building, the location of the Digital Design Laboratory

ECE 2031 is a 2 credit ECE laboratory class and is a requirement for both electrical engineering and computer engineering majors.[1] ECE 2031 is effectively the laboratory class for ECE 2020, and it introduces students to design and implementation methods for digital systems.

ECE 2031 is also a requirement for the systems and architecture and devices threads in computer science.[2][3]

Topic List[edit | edit source]

  • CAD Tools
  • Logic Synthesis using an HDL
  • HDL models of basic gates and logic operations
  • Combinational design using multiple methods: primitive gates, schematic capture for FPGAs, and VHDL
  • HDL based simulation and synthesis with FPGAs
  • Examination of real timing issues on hardware using timing simulation, oscilloscope, and logic analyzer
  • State machine specification, design, and simulation
  • State machine implementation with multiple methods
  • Design verification with logic analyzer
  • HDL models of data storage elements
  • ROM and RAM implementations on FPGA boards
  • Hardware design of a simple computer with ALU, registers, control unit, memory, instructions, and I/O
  • HDL-based simple computer simulation and implementation on FPGA board
  • Machine language and assembly language programming for the simple computer
  • Simulation and implementation of programs on the FPGA board
  • Final design project problem specification (examples: video game, control application, robot, or contest)
  • Hardware and tools available to solve the final design project problem
  • Project engineering issues: top-down vs. bottom-up design, hierarchical decomposition, and modularity

This topic list is from spring 2019.[1]

Workload[edit | edit source]

Labs are released weekly and must be checked off by undergraduate teaching assistants. Pre-lab quizzes are administered prior to lab check offs.

Emphasis is placed on developing technical communications skills; laboratory reports are graded to strict formatting and content standard. The semester concludes with a team project, requiring cooperation with a group of three to four other students.

Registration[edit | edit source]

ECE 2031 is not a linked course.

Resources[edit | edit source]

  • Course Website: includes pre-lab and lab guides; lab checkoffs are done through this website.

References[edit | edit source]