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== Overview ==
{{DISPLAYTITLE:ECE 2031 - Digital Design Laboratory}}
 
 
ECE 2031 is a 2 credit hour ECE laboratory class, and is a requirement for both [[electrical engineering]] and computer engineering majors.<ref>https://www.ece.gatech.edu/courses/course_outline/ECE2031</ref>
[[File:College of Computing Building, Georgia Tech.jpg|alt=A large brick building with pavilion.|thumb|The College of Computing Building, the location of the Digital Design Laboratory]]
 
'''ECE 2031''' is a 2 credit ECE laboratory class and is a requirement for both [[Electrical_Engineering |electrical engineering]] and [[Computer_Engineering |computer engineering]] majors.<ref name=":0">https://www.ece.gatech.edu/courses/course_outline/ECE2031</ref> ECE 2031 is effectively the laboratory class for [[ECE 2020]], and it introduces students to design and implementation methods for digital systems.
 
   
 
ECE 2031 is, in effect, the laboratory class for [[ECE 2020]] and introduces students to design and implementation methods for digital systems. Labs are released weekly and must be checked off by undergraduate teaching assistants. Pre-lab quizzes are administered prior to lab check offs.
ECE 2031 is also a requirement for the [[Systems and Architecture|systems and architecture]] and [[devices]] threads in [[Computer Science|computer science]].<ref>https://www.cc.gatech.edu/content/systems-architecture</ref><ref>https://www.cc.gatech.edu/content/devices</ref>
 
== Topic List ==
 
* CAD Tools
 
* Logic Synthesis using an [[wikipedia:Hardware_description_language|HDL]]
 
* HDL models of basic gates and logic operations
 
* Combinational design using multiple methods: primitive gates, schematic capture for [[wikipedia:Field-programmable_gate_array|FPGA]]<nowiki/>s, and VHDL
 
* HDL based simulation and synthesis with FPGAs
 
* Examination of real timing issues on hardware using timing simulation, oscilloscope, and logic analyzer
 
* State machine specification, design, and simulation
 
* State machine implementation with multiple methods
 
* Design verification with logic analyzer
 
* HDL models of data storage elements
 
* ROM and RAM implementations on FPGA boards
 
* Hardware design of a simple computer with ALU, registers, control unit, memory, instructions, and I/O
 
* HDL-based simple computer simulation and implementation on FPGA board
 
* Machine language and assembly language programming for the simple computer
 
* Simulation and implementation of programs on the FPGA board
 
* Final design project problem specification (examples: video game, control application, robot, or contest)
 
* Hardware and tools available to solve the final design project problem
 
* Project engineering issues: top-down vs. bottom-up design, hierarchical decomposition, and modularity
 
This topic list is from spring 2019.<ref name=":0" />
 
== Workload ==
 
Labs are released weekly and must be checked off by undergraduate teaching assistants. Pre-lab quizzes are administered prior to lab check offs.
 
   
Emphasis is placed on developing technical communications skills; laboratory reports are graded to strict formatting and content standard. The semester concludes with a team project, requiring cooperation with a group of three to four other students.
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Emphasis is placed on developing technical communications skills; laboratory reports are graded to strict formatting and content standard. The semester concludes with a team project, requiring cooperation within a group of three to four other students.
== Registration ==
 
ECE 2031 is not a [[Linked Course|linked course]].
 
   
== Resources ==
 
   
* [https://powersof2.gatech.edu/ddl/index.html Course Website]: includes pre-lab and lab guides; lab checkoffs are done through this website.
 
   
==References==
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=== Topics ===
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As of Spring 2021, the topics covered in the class were:
<references />
 
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[[Category:Courses|^ECE^ECE]]
 
 
# CAD Tools
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# Logic Synthesis using an HDL
 
# HDL models of basic gates and logic operations
 
# Combinational design using multiple methods: primitive gates, schematic capture for FPGAs, and VHDL
 
# HDL based simulation and synthesis with FPGAs
 
# Examination of real timing issues on hardware using timing simulation, oscilloscope, and logic analyzer
 
# State machine specification, design, and simulation
 
# State machine implementation with multiple methods
 
# Design verification with logic analyzer
 
# HDL models of data storage elements
 
# ROM and RAM implementations on FPGA boards
 
# Hardware design of a simple computer with ALU, registers, control unit, memory, instructions, and I/O
 
# HDL-based simple computer simulation and implementation on FPGA board
 
# Machine language and assembly language programming for the simple computer
 
# Simulation and implementation of programs on the FPGA board
 
# Final design project problem specification (examples: video game, control application, robot, or contest)
 
# Hardware and tools available to solve the final design project problem
 
# Project engineering issues: top-down vs. bottom-up design, hierarchical decomposition, and modularity
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=== How it Fits into the Curriculum ===
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ECE 2031 is a requirement for EE and CmpE majors. It is a prerequisite for [[ECE 3005]], [[ECE 3006]], [[ECE 3040]], [[ECE 3043]], [[ECE 3056]], [[ECE 3150]], [[ECE 4180]], [[ECE 4452]], [[ECE 4550]], [[CS 3220]], and [[CS 3651]].
 
== Current Registration Info ==
 
ECE 2031 is not a [[linked course]].
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=== Prerequisites ===
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Two prerequisite options exist for ECE 2031:
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# ([[ECE 2020]] or [[ECE 2030]]) AND ([[ECE 2035]] or [[ECE 2036]] or [[CS 1372]]
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# [[CS 2110]]
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=== AP/IB Credit ===
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No AP or IB credit is available for this course.

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